_Posted on April 17, 2024_ ##### Introduction When processor recieves power, how does it know what to do, and what does it do? This is the question I seek to answer to some extent in a series of posts. I attempt to do this with as little unreduced abstraction as possible and so begin this exploration with how the initial voltage signal is handled by Power-on Reset (POR). All the specific examples I provide are based on the [RP2040](https://www.raspberrypi.com/products/rp2040/) and the related details are taken from the [RP2040 datasheet](https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf) ##### Power-On Reset Sequence Here is the schematic associated with the RP2040 chip-level reset functionality which we discuss below: ![[20240417_19h23m52s_grim.png]] Every computer processor has a set of conductive pins for echanging signal with the external world. One of these pins is typically known as the `RUN/RESET` pin, which is used to signal a reset to the processor. Another of these pins is the `DVDD` pin, which supplies the voltage signal to the processor. When initially receiving power, the processors `DVDD` pin is supplied voltage, and `RUN/RESET` is set high. However, note that in the schematic, `RUN/RESET` is tied to an AND gate which blocks this signal from being immediately recieved by `rst_n_psm` and `rst_n_dp`. When set high, `rst_n_psm` and `rst_n_dp` hand off control to the [[Power on State Machine (Booting Pt2)|Power on State Machine]] to initiate the boot control processes. In order to activate this AND gate, the `_por_n` signal must be set high in addition to the `RUN/RESET` pin. The logic for this is controlled by a Power-on Reset module. When the processor `DVDD` pin recieves voltage, the POR circuit is activated. After initially recieving signal at the desired voltage level (`V_POR`), the POR circuit waits for a certain amount of time, determined by a constant parameter `T_POR`. If all is good, it sets `_por_n` high. On the [RP2040](https://www.raspberrypi.com/products/rp2040/), `T_POR` is $10\mu s$, and `V_POR` is the range $[.924V,.99V]$. After these thresholds are reached, both `_por_n` and the `RUN/RESET` pin are set high and so `rst_n_psm` and `rst_n_dp` are signaled and the reset state is no longer active. The internal [[Power on State Machine (Booting Pt2)| Power on State Machine]] will now handle the remaining setup. Note that I did not mention `psm_restart`. This is used for debugging purposes. When it is set low, the `rst_n_psm` goes into reset mode, while `rst_n_dp` stays as it is. This is effectively a failure mode which allows a debug probe to load code while the processor is in a safe state.